Source : Free On-Line Dictionary of Computing

segmented address space
     
         The {brain damaged} addressing scheme used on
        the {Intel 8086} and later Intel {microprocessors} (and maybe
        others(?))  where all memory references are formed by adding a
        16-bit offset to a 16-bit base address held in one of four
        segment base registers.  Each instruction has a default
        segment (code (CS), data (DS), stack (SS), ? (ES)) which
        determines which segment register is used.  Special prefix
        instructions allow this default to be overridden.
     
        The effect is to segment memory into blocks, of 64 {kilobytes}
        in the case of the Intel processors.  Blocks may overlap
        either partially or completely, depending on the contents of
        the segment registers but normally they would be distinct to
        give access to the maximum total range of addresses.  In this
        case the scheme does provide some degree of {memory
        protection} within a single process since, for example, a data
        reference cannot affect an area of memory containing code.
        However, compilers must either generate slower code or code
        with artificial limits on the size of {data structures}.
     
        Opposite: {flat address space}.  See also {addressing mode}.
     
        (1996-12-21)